It has been a recent trend in dynamic random access memory (DRAM) to increase the density of DRAM integrated circuits. However, as higher density DRAM cells are developed, the area available for capacitors that are used in the DRAM cells decreases. In order to decrease the area of capacitors while maintaining reliability standards, it is important to be able to maintain the capacitance of each capacitor while decreasing its area. Recently, capacitors having a three-dimensional structure have been suggested to increase cell capacitance. Such capacitors include, for example, double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors. In addition, where a polysilicon storage node is used, capacitance can be increased by selectively forming hemispherical grain polysilicon (HSG) on the polysilicon layer.
One of the most popular types of capacitors is the crown capacitor that incorporates HSG formation on the crown portion of the polysilicon. A typical prior art process flow for forming a HSG enhanced crown capacitor involves the formation of a polysilicon plug extending down through an oxide layer and nitride layer to a contact of a transistor. A second oxide layer is then deposited over the polysilicon plug and the nitride layer. Using conventional photolithography and etching steps, a crown shaped opening is formed in the second oxide layer and nitride layer. An amorphous silicon layer is then deposited over the second oxide layer and into the crown opening. The portion of the amorphous silicon layer that is outside of the crown opening is removed by, for example, chemical mechanical polishing (CMP). Next, selective HSG polysilicon is then grown on the amorphous silicon layer to form the bottom plate of the capacitor. Alternatively, the second oxide layer may be removed prior to formation of the HSG polysilicon. This allows HSG polysilicon to be formed on both the inside and outside of the crown structure.
However, the process for forming HSG polysilicon requires precise control of temperature, pressure, and doping level, which often results in large polysilicon depletion (.apprxeq.15% or larger). The depletion effect reduces the capacitance and results in smaller signal charge storage.
The present invention is directed to an improved method for forming a DRAM crown capacitor using HSG polysilicon.